Designing on-chip networks for throughput accelerators
نویسندگان
چکیده
منابع مشابه
Designing Superconducting Cavities for Accelerators
Rapid advances in the performance of superconducting cavities have made RF superconductivity a key technology for accelerators that fulfil a variety of physics needs: high energy particle physics, nuclear physics, neutron spallation sources, and free electron lasers. New applications are forthcoming for frontier high energy physics accelerators, radioactive beams for nuclear astrophysics, next ...
متن کاملCost-aware Topology Customization of Mesh-based Networks-on-Chip
Nowadays, the growing demand for supporting multiple applications causes to use multiple IPs onto the chip. In fact, finding truly scalable communication architecture will be a critical concern. To this end, the Networks-on-Chip (NoC) paradigm has emerged as a promising solution to on-chip communication challenges within the silicon-based electronics. Many of today’s NoC architectures are based...
متن کاملImproving the Throughput of Asynchronous On-chip Networks with SDM
Asynchronous quasi-delay-insensitive (QDI) NoCs have several advantages over their clocked counterparts. Virtual channel (VC) is the most utilized flow control method in asynchronous routers but spatial division multiplexing (SDM) achieves better throughput performance for best effort traffic than VC. A novel asynchronous SDM router architecture is presented. Area and latency models are provide...
متن کاملDesigning Embedded Multiprocessor Networks-on-chip with Users in Mind
Future embedded Systems-on-Chip (SoCs) designed at nanoscale will likely consist of tens or hundreds of (potentially energy-efficient) heterogeneous cores supporting one or several dedicated applications. For such systems, the Networks-on-Chip (NoC) communication architectures have been proposed as a scalable solution which consists of a network of resources exchanging packets while running var...
متن کاملFlexible On-chip Memory Architecture for DCNN Accelerators
Recent studies show that as the depth of Convolution Neural Networks (CNNs) increases for higher performance in different machine learning tasks, a major bottleneck in the improvement of deep CNNs (DCNNs) processing is the traffic between the accelerator and off-chip memory. However, current state-of-the-art accelerators cannot effectively reduce off-chip feature map traffic due to the limited ...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: ACM Transactions on Architecture and Code Optimization
سال: 2013
ISSN: 1544-3566,1544-3973
DOI: 10.1145/2512429